1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a contact hole which penetrates the area between semiconductor wirings of a semiconductor device.
2. Description of the Prior Art
The trend of rendering semiconductor devices more refined and higher density is still being pushed vigorously, and at present development and trial manufacture of semiconductor devices of ultrahigh degree of integration such as logic devices designed with dimensional reference of about 0.15 xcexcm and memory devices using one giga bit dynamic random access memories (Gb DRAMs) are under development. As for the memory devices, products of 256 Mb DRAMs that are reduced version based on the above design reference are about to be put to practical use. However, accompanying such a refinement of the semiconductor devices, formation method of contact holes that is indispensable for semiconductor element structure is becoming extremely difficult.
Normally, in the manufacture of a semiconductor device, a semiconductor element with fine structure is formed by sequentially laminating on a semiconductor substrate, patterns of metal films, semiconductor films, insulator films, and the like formed of various kinds of material. In laminating patterns for the semiconductor element, it is necessary to align a mask with a lower layer pattern that is formed in the previous process in order to form the next upper layer pattern. Similar situation arises also in the formation of a fine contact hole. For example, in a structure where diffused layers are formed on the surface of a silicon substrate and a multilayer wiring is formed on its upper layer, there arises a need for forming contact holes that pass between first layer wirings that are arranged with a prescribed pitch and reach specified regions of the diffused layers in order to connect electrically second layer wirings to the diffused layers. In the following, such a case will be described by reference to FIG. 7.
FIG. 7 shows sectional views arranged in the order of the manufacturing processes for schematically describing the manufacture of a contact hole of a semiconductor device according to the conventional technique.
As shown in FIG. 7A, a trench element isolation region 102 is formed selectively in a specified region of a silicon substrate 101. Here, the trench element isolation region 102 is formed by the known shallow trench isolation (STI) method.
Next, a diffused layer 103 is formed by an ion implantation and a heat treatment. Then, a first layer-insulating film 104 is formed by deposition of a silicon oxide film by chemical vapor deposition (CVD) method and flattening of the silicon oxide film by a subsequent chemical mechanical polishing (CMP).
Next, first wirings 105 of high melting point metal material are formed with a prescribed spacing. Then, a second layer-insulating film 106 is formed so as to cover the first wirings 105 and the first layer-insulating film 104. The second layer-insulating film 106 is made of silicon oxide similar to the first layer-insulating film 104.
After that, a resist mask 107 is formed by the known photolithography process. Then, a contact hole 108 is formed at a prescribed region of the diffused layer 103 by reactive ion etching (RIE) of the second layer-insulating film 106 and the first layer-insulating film 104 using the resist mask 107 as an etching mask. Here, since the contact hole 108 is formed in the space between parallel first wirings 105, when the separation distance between the wirings gets small, the dimension of the contact hole is reduced accordingly.
Now, in a peripheral circuit part of a semiconductor device such as an application specific IC (ASIC), it becomes also particularly important to dispose, in high density, wirings that are formed on the upper layer of an active element like a MOS transistor. For this reason, when the reference of design dimension of the semiconductor device becomes about 0.15 xcexcm, the pitch of the first wirings formed of a high melting point metal such as tungsten is designed to be about 0.5 xcexcm, approaching the limit of the fine processing. In this case, the line width of the first wirings 105 is 0.15 xcexcm and the space between the wirings is 0.35 xcexcm. The size of the contact hole is about 0.15 xcexcm. Here, the margin for the mask alignment in the photolithography process becomes about 0.1 xcexcm.
Next, as shown in FIG. 7B, a barrier metal layer 109, comprising a titanium silicide layer formed only on the surface of the diffused layer 103, and a titanium nitride layer that covers the inner wall of the contact hole 108 and the top of the second layer-insulating film 106, is formed in a specified region of the diffused layer 103 that has the contact hole 108 formed above it.
Next, a contact plug 110 comprising normally of tungsten is buried on the barrier metal layer 109 formed in the contact hole part 108. Tungsten here is deposited by CVD and is then formed by being buried in the contact hole 110 by CMP.
Next, a second wiring 111 to be adhered to the barrier metal layer 109 and the contact plug 110 is formed.
In this way, a portion of the semiconductor device having the first wirings 105 and the second wiring 111, and having a dimension of the contact hole 108 for connecting the diffused layer 103 and the second wiring 111 that is constrained by the space between the first wiring 105, is formed.
Moreover, although not shown, a memory device such as a DRAM has a structure in which a lower electrode of a capacitor constituting a memory cell is connected to a diffused layer via a contact hole provided between parallel word lines or parallel bit lines. In this case, the parallel word lines or parallel bit lines correspond to the first wirings 105 and the lower electrode corresponds to the second wiring 111 in FIG. 7.
As described above, a photolithography process is required in order to open a contact hole of the semiconductor device. In the photolithography process, it is indispensable to align a mask with the lower layer pattern formed in the preprocess, namely, the first wiring pattern. For this reason, in the conventional formation of a contact hole, it is necessary to secure a marginal region for aligning a mask in the arrangement of the semiconductor device. The marginal region required for aligning the mask becomes a significant hindrance factor to the enhancement of the arrangement density of the semiconductor element, forming a large bottleneck toward higher integration or higher density of the semiconductor device.
The effect of the marginal region on higher integration or higher density of the semiconductor device is the more significant as the dimensional reference of the semiconductor device is the smaller. In particular, in a memory device such as a DRAM the effect of the marginal region is conspicuous because there is involved a large number of contact holes.
Objects of the Invention
It is an object of the present invention to provide a method which resolves the problems described in the above and enables to form contact holes in self-alignment with wirings in a semiconductor device having a multilayer wiring. Moreover, it is another object of the present invention to facilitate the formation and enhance the reliability of the self-aligned contact holes in order to apply the method to mass production of the semiconductor device.
Summary of the Invention
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first layer-insulating film of a first dielectric to be adhered to a diffused layer formed on the surface of a semiconductor substrate or to a lower wiring formed on the semiconductor substrate, a step of disposing mutually parallel upper wirings on the first layer-insulating film and forming a protective insulating film of second dielectric with etching rate smaller than that of the first dielectric on the top face and the side faces of the upper wirings, and forming a contact hole reaching the diffused layer or the lower wiring by penetrating the first layer-insulating film by means of a dry etching that uses the protective insulating film as a part of an etching mask.